Makefile

The core concept in Makefile is the target, the produced result of a build.

If you compile a program you run

gcc prog.c

where the argument of the command is the source. But when using make, you run

make prog.o

with the make file

%.o : %.c
    gcc %.c

You use the build target as the argument in your command line.

All

the first target in a makefile is the default, i.e. it will be built when you type make without any arguments. It doesn't really matter what you call it. all or nothing.

When building a target, make first prepares the ingredient. That means, it will build the dependency first when it tries to build a target.

a: c
    echo a

b:
    echo b

c: b
    echo c

With the makefile listed above, a is the first target that will be built when you run make in the same folder as the makefile. To build a, the Make program will try to build c. But c again depends on another target b, so Make then goes to build b.

If a another target is used as a ingredient, make will think that needs to be built forehand because it has no idea whatsoever if the ingredient is ready. On the other hand, if an actual file is used as an ingredient, make can determine if that file is updated. If not, make will not start the building because it thinks it will not build anything new.

make: Nothing to be done for '<target_name>'.

Similarly, if the target (a file) already exists, make can also refuse to build. But this only applies when the target is a file. To explicitly tell make that your target is not a file even though it may coincides with a file's name, you .PHONY.